1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory banks (i.e., storage units which are individually controlled), in particular, one having a plurality of memory blocks each of which includes a plurality of memory banks.
This application is based on Patent Application No. Hei 11-94203 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 12 shows the general structure of a conventional semiconductor memory device. In the following explanations, it is assumed for convenience that the semiconductor memory device is a DRAM (dynamic random access memory) having a storage capacity of 256 Mbit. This semiconductor memory device consists of 32 banks indicated by reference numerals Ba0 to Ba31 in FIG. 12. That is, in comparison with the SDRAM (synchronous DRAM) which generally consists of 4 banks or the like, the memory device shown in FIG. 12 includes a larger number of banks. The reason for dividing the whole memory area into a plurality of banks follows: In the DRAM or the like, the operation of storing or deleting data in or from the internal memory cells is performed using the charge or discharge process; thus, the operation speed in the semiconductor memory device cannot be as high as the transfer speed of the bus connected to the memory device. Therefore, the memory cell array in the semiconductor memory device is divided into a plurality of banks so as to perform a parallel process, thereby virtually performing a high-speed operation having a speed as high as the bus operation.
Each bank can be regarded as a logically independent memory, and as explained above, while the banks are activated in turn, serial data input/output operation is performed with respect to each target cell, thereby realizing a high-speed general operation. As with general DRAMs, the semiconductor memory device shown in FIG. 12 has a two-dimensional memory cell arrangement. In order to designate one of the memory cell arrays, the address signal supplied to the semiconductor memory device includes a bank address for designating a bank, a row address for designating a row in the X direction, and a column address for designating a column in the Y direction. The upper portion of the address signal is assigned to the bank address. The target memory cell is accessed by designating the target bank using the bank address, and then designating the memory cell using the row and column addresses.
More specifically, the semiconductor memory device shown in FIG. 12 has 4 blocks, each consisting of 32 banks. For example, the areas indicated by reference numerals 1-1 and 1-2 form a single block. In area 1-1 or 1-2, 32 Mbit (256 Mbit/8) memory cells are integrated, and each area is called a "memory cell array block" in the following explanations. Memory cell array blocks 1-1 and 1-2, 1-3 and 1-4, 1-5 and 1-6, and 1-7 and 1-8 respectively form pairs, and 32 banks Ba0 to Ba31 are assigned to each pair.
Each memory cell array block has a ".times.4 bit" structure. When a specific address is designated or read out, 32 bit data is output from 32 I/O lines. In FIG. 12, each arrow indicates "4 I/O", and eight "4 I/O" (i.e., 4 I/O.times.8) arrows output from each memory cell array block indicates the above operation. Accordingly, if data is read out from a bank of the memory cell array blocks 1-1 and 1-2, a 32 bit data is output in total. The 32 bit data is then parallel-serial converted. The data from the memory cell array blocks 1-1 and 1-2 is combined with a 32 bit data from the memory cell array blocks 1-5 and 1-6, so that a 8 DQ.times.8 cycle data is output via circuit block 6 (explained later) to the outside of the device. A similar operation is performed in the memory cell array blocks 1-3 and 1-4 and the memory cell array blocks 1-7 and 1-8.
Circuit blocks 2-1 to 2-4 are provided between the two memory cell array blocks of each of 4 pairs. Each circuit block comprises a data amplifier (see "DA" in FIG. 12) for amplifying data read out from the memory cell array via a sense amplifier (not shown) and the like, a write amplifier (see "WA" in FIG. 12) used when data is written in the memory cell array, a column decoder for decoding the column address of the relevant memory cell array block, and so on.
Reference numerals 3-1 to 3-8 indicate row decoders (see "Row Dec." in FIG. 12) for decoding the row address in the address signal and outputting a decoded signal obtained by the decoding operation. These row decoders 3-1 to 3-8 correspond to each memory cell array block.
The circuit blocks 4-1 and 4-2 are arranged in the upper and lower sides of circuit blocks 5 to 7 (explained later). Each of the circuit blocks 4-1 and 4-2 comprises row pre-decoding circuit (see "Row pre dec." in FIG. 12) for pre-decoding the row address before the decoding operation of the row decoder, and a redundancy circuit (see "Row red." in FIG. 12) for performing a redundancy process for recovering a disordered memory cell array in the row direction.
The circuit block 5 comprises a booster circuit (see "Vboot" in FIG. 12) generally used when the word line is activated, a fuse (see "Fuse" in FIG. 12) used for the redundancy process, a reference potential generating circuit (see "Vref" in FIG. 12) for generating a reference potential used for reducing the internal voltage, and so on.
The circuit block 6 comprises an input/output interface circuit (see "I/F" in FIG. 12), a circuit for adjusting the skew of the clock used in the semiconductor memory device (see "DLL (delayed lock loop)" in FIG. 12), a known input/output pad (see "Bonding Pad" in FIG. 12), and so on.
The circuit block 7 comprises the above "Vboot", "Fuse", and a circuit for generating a substrate potential (see "BBG (back bias generator)" in FIG. 12), and so on.
FIG. 13 is an enlarged view showing the circuit related to memory cell array block 1-1. In a general SDRAM or the like, the row decoder, column decoder, sense amplifier, and the like are separately provided for each bank. In contrast, in the semiconductor memory device as shown in FIGS. 12 and 13, a row decoder is provided for 16 banks (i.e., Ba0 to Ba15, or Ba16 to Ba31). Additionally, as shown in FIG. 13, sense amplifier area 10 is provided between the banks. In the area 10, a sense amplifier (may be abbreviated as "S/A", hereinbelow) for reading out data from the memory cell array, and the like are provided.
A bank selecting logic circuit (not shown) is provided close to the row decoder 11. The column bank selecting signals CBS0 to CBS15 generated by the bank selecting logic circuit are respectively supplied to the banks Bank0 to Bank15, and each bank selecting signal can be independently made effective, thereby activating the corresponding bank. The bank selecting logic circuit is provided in the circuit blocks 4-1 and 4-2 shown in FIG. 12. When the bank Bank1 is being activated, the bank selecting operation using the bank selecting signals CBS1 is performed in the sense amplifier areas adjacent to Bank1. These column bank selecting signals CBS0 to CBS15 can be obtained by decoding the bank address included in the above-explained address signal. As later explained, each column bank selecting signal uses two signal lines (inverted/non-inverted); however, a single signal line is described in FIG. 13 for convenience.
The row decoder 11 decodes the row address included in the address signal, thereby selecting one of the word lines WL indicated by broken lines in FIG. 13. The column decoder 12 decodes all bits (7 bits in the later-explained embodiment of the present invention) of the column address included in the address signal, thereby selecting one of column selecting signals YSW (indicated by thick lines in FIG. 13) by using a column switch (not shown) corresponding to each signal. Accordingly, a memory cell is selected by using the bank address, row address, and column address included in the designated address signal.
Here, the memory cell array block 1-2 has a structure similar to that of the memory cell array block 1-1, where the differences are (i) banks Bank16 (i.e., Ba16) to Bank31 (i.e., Ba31) are included (the block 1-1 includes banks Bank0 (i.e., Ba0) to Bank15 (i.e., Ba15)), and (ii) the blocks 1-1 and 1-2 have a mirror-image arrangement with respect to the "boundary" row decoder 12. In the above explanation, only the bank Bank1 is activated; however, in the actual operation, a plurality of banks may be activated in turn and the banks may be selected in turn with a specific interval. For example, first, only bank Bank0 is activated, and a memory cell in the bank is selected using the row address and column address in the designated address signal so as to input or output data, and after a specific elapsed time, bank Bank2 is also activated while the bank Bank0 is still activated, and a memory cell in Bank2 is selected.
FIG. 14 is a circuit diagram showing the structure of the column selecting circuit provided in the sense amplifier area 10 shown in FIG. 13. In FIG. 14, reference numerals 15 to 18 indicate N-channel transistors (the transistor may be abbreviated as "TR", hereinbelow), and reference symbol CBS indicates the above-explained column bank selecting signal, reference symbol CBSB indicates an inversion signal of the column bank selecting signal CBS, reference symbol YSW indicates the column selecting signal indicated by the thick lines in FIG. 13, reference symbol GND indicates the earth (or ground) potential, reference symbol D indicates a digit line connected to the sense amplifier (not shown), reference symbol DB indicates a signal line through which an inversion signal of the signal passing through the digit line D is transmitted, and reference symbols I/OT and I/ON indicate signal lines through which a signal through the I/O line connected to the I/F control circuit in circuit block 6 in FIG. 12, and an inversion signal thereof respectively pass.
According to the circuit structure as shown in FIG. 14, when the target bank is not activated and the column bank selecting signals CBS and CBSB respectively have "L" (low) and "H" (high) levels, TR15 is on (i.e., in the On state) while TR 16 is off (i.e., in the Off state). Therefore, both gates of TR 17 and TR 18 are in the "L" level, so that digit lines D and DB are not connected to signal lines I/OT and I/ON. If the target bank is being activated and the column bank selecting signal CBS and CBSB are respectively in the "H" and "L" levels, then TR 15 is off while TR 16 is on, so that the potential of the column selecting signal YSW is applied to the gates of TR 17 and TR18. In this operation, if the column corresponding to the column selecting circuit is being selected, the level of the column selecting signal YSW becomes high and both TR17 and TR18 are on. As a result, the digit lines D and DB are respectively connected to signal lines I/OT and I/ON, so that the potential of the bit line with respect to each of the digit lines D and DB is transmitted to the relevant I/O line and is output to the outside of the semiconductor memory device.
As explained above, in a conventional semiconductor memory device, the column decoder 12 is used in common by 16 banks. In addition, the column selecting signal YSW is also arranged over a plurality of banks on the memory cell plate, that is, the signal YSW is also used in common by those banks. Accordingly, when a column is selected using the column selecting signal YSW, the word line WL selected by the row decoder 11 is activated in all 16 banks. Therefore, one of the column bank selecting signals CBS0 to CBS15 is made effective, thereby further selecting one of the 16 banks, which is subjected to the data input/output operation. Therefore, in the conventional semiconductor memory device, the column bank selecting signal line is arranged in the sense amplifier area 10. However, in such an arrangement, the sense amplifier area 10 must be larger, and thus the total area of the chip is increased.
The conventional column selecting circuit as shown in FIG. 14 has the following problem. In the circuit, when the column bank selecting signal CBS is "H", the signal level thereof must be higher than the power supply voltage Vcc (not shown) which is generated inside the semiconductor memory device. If this condition is not satisfied, when the column selecting signal YSW is decreased to the power supply voltage Vcc according to the voltage drop caused by TR16, signal transmission to the gates of TR17 and TR18 may fail.
In order to prevent such a problem, in the conventional semiconductor memory device, the levels of the column bank selecting signals CBS and CBSB are set higher than the level of the power supply voltage Vcc. As the power source to satisfy this condition, the above-described booster circuit (see "Vboot" in FIG. 12) is used. However, the booster circuit Vboot is originally used only for boosting the word line; thus, to use the booster circuit for another use increases power consumption, and the boosting capability of the booster circuit has a limit.
Additionally, in the conventional semiconductor memory device, the arrangement of the column selecting signal YSW lines and the I/O lines causes the following problem. FIG. 15 is a diagram for explaining this problem. This diagram is an enlarged view of the neighboring area (as shown in FIG. 13) of the memory cell array block 1-1 shown in FIG. 12. In the figure, data amplifier 19 (see "DAMP" in FIG. 15) relates to the structure of FIG. 12, and is provided for amplifying the signal level of data read out to the I/O lines (i.e., I/OT and I/ON) from the sense amplifier (not shown).
As shown in FIG. 15, in the conventional semiconductor memory device, the column selecting signal YSW lines and I/O lines are arranged parallel to each other, more specifically, parallel metallic wiring lines are arranged in a layer over a long distance (actually, approximately 4 to 5 mm) from the column decoder 12 to the left end (the bank Bank0 side) of the memory cell array block. In such an arrangement, the crosstalk due to the coupling of the wiring between the lines (i.e., capacitance C in the same wiring layer in FIG. 15) cannot be disregarded.
The above problem will be further explained in detail. It is assumed that the word line WL connected to a memory cell is activated and the sense amplifier for sensing data stored in the relevant memory cell is activated, and the stored data is amplified by the sense amplifier and is output to digit lines D and DB (see FIG. 14). In the next step, the column corresponding to the memory cell is selected, and the level of the column selecting signal YSW is changed from "L" to "H". Simultaneously, the digit lines D and DB are connected to the I/O lines (i.e., signal lines I/OT and I/ON) according to the function of the column selecting circuit shown in FIG. 14, and data on the digit lines D and DB is transmitted to the I/O lines so that the signal level of each I/O line is changed. Accordingly, the data amplifier 19 shown in FIG. 15 receives a difference potential between the signal lines I/OT and I/ON (functioning as the I/O lines) and further amplifies this potential.
The above I/O lines are arranged over a long length from an end of the memory cell array block (i.e., the bank Bank0 side in FIG. 15) to the other end (i.e., the data amplifier 19 side); thus, the length of the wiring is long and its load capacity is large. Therefore, the signal level of each I/O line input into the data amplifier 19 is very small, and the data reading period is short. On the other hand, the amplitude of the column selecting signal YSW is larger than the amplitude of the data on the I/O lines. Therefore, if the column selecting signal YSW is changed when the data signal on the I/O lines rises, then the crosstalk due to the column selecting signal YSW directly affects the I/O lines. That is, even when the signal lines I/ON and I/OT are preferably balanced, the crosstalk may affect the signal lines and causes an undesirable change of the signal lines. Therefore, the data output from the data amplifier 19 may be delayed, and the data amplifier 13 may read erroneous data according to the delay.
In order to prevent the above problem, the crosstalk due to the coupling between the column selecting signal YSW lines and the I/O lines should be prevented as much as possible. For example, the resistance of the column selecting signal YSW lines and the I/O lines may be decreased. However, in this case, the wiring line would have to be thicker and thus the spacing between the wiring lines should be narrower; thus, a specific pitch of the wiring lines cannot be obtained. Therefore, this example for solving the above problem is not preferable in practice.
Additionally, in the conventional arrangement as shown in FIG. 15, the I/O lines are connected via column decoder 12 to data amplifier 19; thus, the layout design (for making a mask) in the vicinity of the column decoder 12 is difficult. For example, it may be difficult to make the I/O lines pass through the column decoder 12 according to a layout design. In such a case, the I/O lines should make a detour, thereby requiring a larger width or area for wiring. In addition, as explained above, four pairs of I/O lines (i.e., 8 I/O lines) are output from the memory cell array block; thus, the above-described problem is much more serious. That is, the conventional arrangement has a serious problem from the viewpoint of the layout.
The conventional semiconductor memory device also has the following problem. FIG. 16 is a diagram for explaining the problem.
The word lines WL indicated by broken lines in the figure are the same lines as shown in FIG. 13, and "SAA" indicates a signal line of the sense amplifier activating signal for making the sense amplifier (not shown) start the data sensing operation. Here, a timing limit is present between the sense amplifier activating signal SAA and the column selecting signal YSW. It is assumed that the word line WL is activated and the relevant sense amplifier is activated using the sense amplifier activating signal SAA. Under these conditions, if the column selecting signal YSW is made effective (so as to obtain a sensed result) even though the signal potential of the data output onto the digit lines D and DB (see FIG. 14) has not been sufficiently changed, a problem may occur, for example, the potential of the signal on the digit lines D and DB may be inverted. Therefore, the timing between the sense amplifier activating signal SAA and the column selecting signal YSW should be adjusted so as to make the column selecting signal YSW effective after the data of the memory cell is sufficiently sensed.
As shown in FIG. 16, in the conventional semiconductor memory device, the word lines WL and the sense amplifier activating signal SAA lines indicated by the broken lines are arranged parallel to each other (i.e., along the vertical direction in the figure). As for the delay on the wiring lines, elliptic area A16 lastly receives the signal for driving the word line and the sense amplifier activating signals SAA when observed from the row decoder 11 side. That is, this area A16 is the far end of the word line and the far end of the sensing operation signal. On the other hand, area B16 is the first area which receives the above signals. That is, this area B16 is the near end of the word line and the near end of the sensing operation signal. In addition, when observed from the column decoder 12, area B16 lastly receives the column selecting signal YSW (that is, this area is the far end of the column selecting signal YSW). On the other hand, area A16 first receives the column selecting signal YSW (that is, this area is the near end of the column selecting signal YSW).
That is, the area A16 lastly receives the sense amplifier activating signal SAA and first receives the column selecting signal YSW, so that the period from the time when the sense amplifier activating signal SAA is activated to the time when the column selecting signal YSW is activated is shortest. Therefore, the temporal margin from the time when the sense amplifier activating signal SAA becomes effective to the time when the column selecting signal YSW becomes effective must be determined based on the area A16. In contrast, the area B16 first receives the sense amplifier activating signal SAA and lastly receives the column selecting signal YSW. Therefore, if the temporal margin is designed based on the condition of area A16 as described above, then in the area B16, the column selecting signal YSW may not become effective for a long time even if the sensing operation had already been completed a sufficient time before; thus, an undesirable waiting time occurs.
As explained above, in the conventional arrangement, the period from the start of memory-cell sensing to the column selection is not fixed according to each position on the memory cell array block; thus, an extra margin is necessary, and it is difficult to operate the semiconductor memory device with high speed. If the driving capability of the driver for driving the word lines, or the like, is improved and the relevant resistance is thus lowered, the above problem related to the difference between the far and near ends can be reduced. However, the area occupied by the driver is increased in proportion with the improvement of the driving capability, and the chip size must be increased.